Abstract
A 40 Gb/s half-rate linear phase detector IC for NRZ data, implemented in a 200 GHz f/sub T/, InP DHBT process, with a novel architecture, is described. The IC can be used for clock recovery or jitter measurement. The new architecture has less critical internal timing, and better speed and linearity than previous phase detectors. Half rate operation doubles the allowable propagation delay. Dual outputs alternate in time and combine linearly, allowing overlap without error, resulting in greater linear range. Operation at any rate is possible because no rate-specific delay lines are used. The intrinsic jitter for a 40 Gb/s 2/sup 31/-1 PRBS pattern is 50 mUl pk-pk in a 320 MHz bandwidth.
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