A framework to improve programmability of low power many-core processor for scalable DSP application

Abstract

Embedded and ubiquitous sensors are driving industry to look for low power solutions for complex DSP algorithms; system engineers are also looking for upgradable capability to higher throughput and algorithm enhancements. Many-core, parallel architectures seem to be a solution to meet these interests at the same time. However it introduces a challenging problem: the programmability of a many-core processor is generally perceived by industry as difficult and inefficient. A new framework is proposed to solve this challenge. This framework includes a dataflow programming methodology at the top level design, and an embedded automatic cell generator to solve the module level data parallel problem. Data flow programming methodologies avoid explicit synchronization among modules; the data flow naturally drives the synchronization. At the module level, a cell generator handles application-specifics, including data dependencies, amount of parallelization required to achieve desired throughput and complete memory management, and generation of a library. This framework provides a path to quickly develop a DSP algorithm on a many-core processor, to achieve a scalable, higher throughput, and lower power solution. The framework demonstrated by this paper has been applied to various DSP algorithms to efficiently parallelize and scale for different through-put or power requirement, on Coherent Logix's low-power 100 core hx3100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> processor based on HyperX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> technology.