A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA

Abstract

The demands for both increased performance and low power consumption on computing devices are outpacing technological improvements. Approximate computing is a design paradigm to leverage inherent error resilience of applications and trades in quality to reduce resource usage. Numerous approaches for approximation on FPGAs have been proposed in recent years and combining different methods can increase the resulting benefits in complex systems. Interactions between system components and error propagation necessitate a global design space exploration for the optimization of the approximation parameters. The loss of quality can be assessed by employing application-specific reference error metrics like PSNR or CIELAB ΔE which are well understood by designers and take error propagation implicitly into account. However, using a reference error metric can be very time-consuming, slowing down the design space exploration. To overcome this problem, we propose a framework for fast design space exploration of approximated FPGA designs in which the quality estimation is offloaded to an FPGA-based accelerator while the rest of the design space exploration is handled by a workstation PC. We evaluate the proposed framework on an image processing pipeline which is used to adapt image colors to be displayed correctly on a monitor. Our experiments show that using the accelerator yields similar results for the design in terms of the achieved quality-power trade-off compared to a software-only setup and can speed up the exploration by a factor of over 200x.