A framework for automated testing from VDM-SL specifications

Abstract

Using formal methods in early phases of software life cycle can help avoid specification errors and ambiguities. However, use of formal methods does not guarantee that implementation would conform to specifications. A formal proof of correctness is not justifiable for most software projects because of the cost involved. Therefore, need for rigorous testing is not eliminated by the use of formal methods. In fact, formal methods and testing complement each other. Several researchers have proposed techniques for automatic generation of test cases from formal specifications. However, most of these techniques are based on state space search methods. In this paper, we propose a novel approach to automating generation, sequencing and execution of test cases in a proposed framework. The approach is based on parsing VDM-SL expressions to generate C code as well as test data. The source code is then modified to insert a call to precondition of a function just before the function call itself to ensure that the system is in correct state before an operation is carried out. Finally, the generated test cases are executed on the implementation and results are evaluated by executing code for post-conditions.