A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS

Abstract

Fractional-N digital phase-locked loops (DPLLs) are highly reconfigurable, scalable, and useful for synthesizing clocks with fine frequency resolution for modem RF, mixed-signal and digital VLSI systems. One critical design challenge is the associated fractional-N spurs, which result from the quantization error of the time-to-digital converter (TDC) or delta-sigma modulator when using multi-modulus fractional dividers. Those unwanted spurs can cause degraded deterministic jitter, reciprocal mixing, and undesired spectrum emissions, depending on the actual PLL application. Various techniques have been used to mitigate fractional spurs. One is to apply dithering [1-3] in the input reference path to randomize the periodic phase error pattern, hence reducing spur magnitude. However, the dithering signal also increases the phase noise floor. A two-level dithering scheme [3] has been adopted to limit noise degradation (but with less spur reduction), or a foreground noise-cancellation technique [2] can be applied at the cost of higher complexity without real-time voltage/temperature tracking ability. Alternatively, the technique in [4] directly cancels spurs and avoids elevating the noise floor, but it increases the logic complexity for near-carrier fractional spurs. To resolve those bottlenecks, we dither the input reference clock and leverage an adaptive dither-noise-cancellation loop operating continuously in the background. Thus, it allows for a larger dithering signal with minimal impact on the noise floor, leading to a more randomized phase error pattern and hence lower spur magnitude. The background operation compensates for PVT variation in real time (response time 40dB spur improvement and achieves a worst-case fractional spur of −62.5dBc at 1.83kHz frequency offset, lower than state-of-the-art PLLs applying dither approaches. The jitter and spur fluctuation after dither noise cancellation is within 2% and 2.5dB, respectively, when measured over 6 chips, supply voltage (+/-10%) and temperature (27°-60°C) variations, showing the technique's robustness.