A FPGA-based accelerated architecture for the Continuous GRASP

Abstract

This work proposes a FPGA-based architecture for accelerating the Continuous GRASP (C-GRASP), a prominent metaheuristic for solving continuous optimization problems. Although FPGA implementations have been proposed for other metaheuristics, nothing has been done for C-GRASP. We conduct a comprehensive set of experiments on well-known hard test problems, and compare our FPGA architecture with C-GRASP implementations running on four other architectures: a single-core ARM Cortex A9-based, a single-core Intel i7-based, a multi-core Intel i7-based, and a GPU-based. Experimental results demonstrate that the proposed architecture outperforms the others in terms of performance-to-power-efficiency. For instance, it is on average 3x faster and 15x less power consuming than the single-core Intel i7-based implementation. Moreover, we introduce a model-based method that helps designers with little experience in FPGA development to use our high-performance architecture to optimize their problem. Our solution is a very interesting option for the emerging technology of FPGA-based data centers (e.g, Microsoft’s Catapult project), and also for resource-constrained embedded systems (e.g., drones).