A Four-Way Nested Digital Doherty Power Amplifier for Low-Power Applications

Abstract

This article demonstrates the advantages of a nested digital Doherty power amplifier (PA) to achieve high efficiency in deep power back-off (PBO) for low-power applications. A differential four-way digital Doherty PA (D4DPA) is implemented in a general-purpose 65-nm CMOS process as a proof-of-concept that ideally achieves efficiency enhancement through 9-dB PBO. The PA uses a compact input and output matching network through consolidation of components, and it achieves a peak drain efficiency (DE) of 48% and a system efficiency (SE) of 31% with 7.3 dBm of output power ( $P_{\mathrm{ out}}$ ) and 14 dB of gain at 4.75 GHz. It also obtains a DE of 42% and 20% at 0- and 12.8-dB PBO, respectively, at 5.25 GHz, which corresponds to a $2.2\times $ improvement over normalized class B PA. Finally, RF modulation measurements performed on the PA show that it achieves a DE of 34% and an rms error vector magnitude ( ${\mathrm{ EVM}}_{\mathrm{ rms}}$ ) of −20.5 dB for a 1-MSym/s 16 QAM RF waveform at 5.25 GHz.