A Four-Element 7.5–9-GHz Phased-Array Receiver With 1–8 Simultaneously Reconfigurable Beams in 65-nm CMOS

Abstract

This article presents a four-element 7.5–9-GHz phased-array receiver with 1–8 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes all the input elements to maximize the beamforming gain. To realize a low-power and compact design, the multielement multibeam phased-array architecture features the gm-based variable-gain phase shifter (VG-PS) and the current-sharing active combiner. The VG-PS with 6-bit phase resolution achieves $5.42\times3.62$ mm2 area excluding pads and consumes 860 mW, equivalent to the record low 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.