A Four-Element 500-MHz 40-mW 6-bit ADC-Enabled Time-Domain Spatial Signal Processor

Abstract

Next-generation wireless communication requires phased-array systems with large modulated bandwidths and high energy efficiency, ensuring Gb/s data communication. Conventional phase-shifter-based arrays result in frequency-dependent processing and, therefore, beam-squinting in an array. This work demonstrates a four-element 500-MHz modulated bandwidth true-time-delay-based ADC-enabled spatial signal processor (SSP) with frequency-uniform beamforming, wideband beam-nulling, and multiple independent interference filterings using the Kronecker decomposition. This processor can augment conventional phased-array RF front ends to implement a complete antenna-to-digital solution. The proposed baseband delay-compensating solution in the SSP uses scalable time-domain circuits comprising of time-interleaved voltage-to-time converters followed by asynchronous 6-bit pipeline time-to-digital converters and consumes only 40 mW with a total area of 0.31 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65-nm CMOS technology.