A Formal Approach to Design-Rule Checking

Abstract

This paper describes the development of a layout model and the theoretical basis for a relatively technology-independent, false-error free, hierarchical design-rule checker for VLSI circuit layouts which have Manhattan geometry and are subject to some design-rule simplifications. A flat model of the layout of a VLSI circuit using set theory notation is first defined. Two primitive operations and five primitive set functions are formally defined to process the layout and to form a complete set of primitives in the algebra of design-rule checking. The most widely used design rules can be defined as functions in terms of these primitives. Each design-rule function determines if a geometrical shape on a layer conforms with that rule. Provisions are also made to handle inconsistent design rules (e.g., butting contacts) at some extra cost. Finally, graph theory is employed to extend the flat model to define a hierarchical model for the layout of a VLSI circuit. The hierarchical model has been used as the basis for the development of a hierarchical design-rule checker.