A footprint-constrained efficiency roadmap for on-chip switched-capacitor DC-DC converters

Abstract

This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled SC converter efficiency, where it is found that the efficiency scales inversely with the product of the chip clock frequency and the MOSFET intrinsic delay. Through a derived numerical model of the SC power density, it is shown that a ∼ 0.5 W/mm2 SC density is sufficient to satisfy portable SoC power management needs with over 80% SC efficiency across the International Technology Roadmap for Semiconductors. This is at minimal area penalty by utilizing the nominally required 0.5 nF/mm2 decoupling capacitance for supply integrity.