A folding ADC preprocessing architecture employing a robust symmetrical number system with gray-code properties

Abstract

A folding analog-to-digital converter (ADC) preprocessing architecture based on a new robust symmetrical number system (RSNS) is presented. The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position (gray-code properties). Although the observed dynamic range of the RSNS ADC is less than the optimum symmetrical number system ADC, the RSNS gray-code properties make it particularly attractive for error control. With the RSNS preprocessing, the encoding errors due to comparator thresholds not being crossed simultaneously are eliminated. As a result, the interpolation circuits can be removed and only a small number of comparators are required. Computer generated data is used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Closed-form expressions for the dynamic range are also presented for channel moduli of the form m/sub 1/=2/sup k/-1, m/sub 2/=2/sup k/, m/sub 3/=2/sup k/+1. RSNS ADC circuit design principles are presented. To compare the advantages of the RSNS ADC with previously published results, the transfer function of a 3-channel architecture (k=2) is evaluated numerically using SPICE.