A Flying Capacitor-Based Multilevel Inverter Architecture With Symmetrical and Asymmetrical Configurations

Abstract

In this article, a novel flying capacitor-based multilevel topology is presented to minimize the size and cost. The proposed topology can operate in the symmetrical and asymmetrical configuration of dc sources and produces the 9-level and 25-level output voltage, respectively. The minimized device count, negative polarity voltage generation without auxiliary H-bridge, reduced maximum peak inverse voltage across the switches, and inherent voltage balancing across the floating capacitors are the main advantages of the proposed topology. Two extended topologies are proposed, and various necessary parameters are derived from achieving a higher number of output voltage levels. The effective comparison is furnished in terms of switches, diodes, capacitors, total standing voltage, and cost function to show minimization of device count of the proposed topology against the recent popular topologies. The extensive simulations in MATLAB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\backslash $ </tex-math></inline-formula> Simulink are carried out to study the operation of proposed topology and feasibility is validated through the laboratory experimental tests. The performance of the topology under dynamical variation of frequencies, modulation indexes, and load are studied and respective results are presented.