Abstract
In this work, we propose the Explicit Redundancy Linear Array (EReLA) architecture to provide a highly flexible fault-toleration, which effectively utilizes its rich resources in a functional unit (FU) array for both the error detection and the fail-safe hot-swap after taking a permanent fault. For the preparation of the hot-swap, a self-tuning scheme is proposed specifically to fast locate the precise position of the permanently defective units, which can be either the computational, LD/ST FUs, or the connecting network as well. EReLA can thereby isolates the permanently defective unit at the smallest granularity, which allows more hot-swaps and extends accordingly the lifespan of the whole processor. Given these schemes, EReLA is functionally same to a traditional TMR processor in terms of fault toleration, while the power data of a 180nm prototype EReLA chip has indicated that it incurs far less power consumption than the TMR implementation.
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