A Flexible-Length-Arithmetic Processor Based on FDFM Approach in FPGAs

Abstract

The main contribution of this paper is to present an intermediate approach of software and hardware using FPGAs. More specifically, we present a processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations with flexibly many bits, and implement it in the Xilinx Virtex-6 FPGA. Arithmetic instructions of our processor architecture include addition, subtraction, and multiplication for numbers with variable size longer than 64 bits. To show the potentiality of our processor, we have implemented 2048-bit RSA encryption/decryption by software written by assembly program. The resulting processor uses only one DSP48E1 slice and two block RAMs, and RSA encryption software on it runs in 613.71ms. It has been shown that the direct hardware implementation of RSA encryption runs in 277.26ms. Although our intermediate approach is slower, it has several advantages. Since programs for the proposed processor can be written by software, the development and the debugging are easy. We have also succeeded in implementing 306 processor cores in one Xilinx Virtex-6 FPGA which work in parallel to improve the throughput greatly.