A Flexible Programmable Memory BIST Architecture

Abstract

In the present paper a moderate area programmable memory built-in-self-test (BIST) architecture supporting multiple algorithm loading is proposed. The entire BIST operation is made possible with a cheap low cost tester used for initial loading. The loaded data is decoded and executed by the BIST architecture at high speed since there is no interruption from the tester. This avoids costly high speed interfaces during the execution of the BIST. The proposed BIST architecture can execute all March like algorithms. It supports normal, preset, retention and repair modes of operation. Repair facility is value addition to the proposed design. The proposed programmable BIST architecture is very flexible and cost effective.