A first-in, first-out memory for signal processing applications

Abstract

This paper describes the design and implementation of a First-In, First-Out (FIFO) memory for signal processing applications. The FIFO design allows concurrent input and output of data, both operations requiring one clock period each. The design is based on 4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\mu</tex> NMOS technology and operates with a 8-MHZ clock. The length of the FIFO is programmable, resulting in minimum data ripple-through times, for applications not requiring the full length of the memory. A built-in test scheme incorporated in the design makes the functional verification of the FIFO easy and it gives the memory some self-testing capabilities during operation. The memory size is 128 bytes and occupies 18.5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm^2</tex> silicon area. Memories of larger sizes are easily obtained by cascading FIFO chips.