A FinFET Design for Superior High-Voltage Performance

Abstract

To mitigate the trade-off between breakdown voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> ) and on-resistance (Ron) of high-voltage FinFETs, we propose the DMGFP-FF, in which a high-k field plate (FP) and dual material gate (DMG) are simultaneously applied to a conventional drain-extended FinFET. We analyze electric field, drain induced barrier lowering (DIBL), impact ionization, electron velocity and density of DMGFP-FF and SMG-FF using TCAD simulation. FP induces a charge variation in the drain extension (DE) resulting in electric field dispersion in gate-off state and electron accumulation in gate-on state. DMG forms a step-potential which induces electric field dispersion and DIBL suppression in gate-off state, and accelerates electrons in the channel in gate-on state. Consequently, as DMGFP-FF has high V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> and low Ron, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{V}_{\boldsymbol{\text{BD}}}-\boldsymbol{R}_{\boldsymbol{\text{on}}}$</tex> trade-off is drastically reduced.