A fine-grained many V T design methodology for ultra low voltage operations

Abstract

In this paper, we propose a fine-grained many VT design methodology for ultra low voltage (ULV) operations of CMOS VLSI circuits. The fine-grained many VT transistors can be developed through only layout-level technique (e.g. inverse narrow width effects) in a multi-VT technology without any process modifications. Through SPICE simulations, we confirm that the proposed design methodology can improve performance, energy efficiency and variability of ULV circuits in three important domains, i.e. driving a fixed capacitive load, reducing active leakage energy consumption in non-critical paths, and lengthening short delay paths without energy overhead to aid error detection and correction techniques.