A Federal Approach to Formal Hardware Design Verification

Abstract

Abstract : The goal of this project was to enable the solution of hard formal verification problems - and thereby reduce the cost and improve the quality of advanced hardware designs - by making it possible to combine different verification techniques in flexible ways. This was be accomplished by developing an open software environment that allows various techniques to be combined easily. Various prototype tools were developed to support and use this environment, and results were evaluated on some example designs of interest. There were significant accomplishments in several areas. We developed a better understanding of design and implementation issues in building a environment. SRJ's widely-used PVS theorem prover was modified to provide APIs (application program interfaces) enabling it to be used in a variety of other tools. The enhanced version of PVS was used in the successful verification of hardware and safety-critical systems by other groups. We implemented a general-purpose system of cooperating decision procedures for quantifier-free first-order logic formulas, called SVC. This system integrated several decision procedures into a single framework, and was also used as a software component in several different verification tools, so it was federated at two different levels. The source code for the SVC system is freely available, and the system has been extensively used inside and outside of Stanford. Later, work was begun on re-engineering SVC to be more flexible, powerful, and efficient. We developed and prototyped new techniques for checking table-based specifications of embedded software systems, in the RSML description language. We analyzed and found some problems in an RSML specification of the safety-critical TCAS collision avoidance system. A tool for doing approximate symbolic model checking was prototyped and applied to an example design from another group at Stanford.