A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing

Abstract

The analog calculating circuits perform with benefits on fewer transistors and interconnections, high speed, and low power for the approximate computing applications, but suffer from the poor programmability. This work explores an architecture of programmable analog circuitry to calculate arbitrary functions with acceptable accuracy. The support vector regression (SVR) algorithm is employed to emulate any specific functions. A set of analog circuits are designed for implementing the regression network, in which the relevant parameters are dynamically programmable to specify the target function. An efficient scheme of SVR algorithm is proposed to shrink the scale of regression network and circuit implementations. In this manner, the arbitrary functions between two operands can be computed in real-time with only 600 transistors. The demo processor, called Analog Calculation Unit (ACU), is designed and simulated in a standard CMOS technology for proof-of-concept. From the circuit simulation results, the proposed ACU calculates all the target functions in real-time with the error less than 4.3 %. The performances over speed, functions, and hardware efficiency of proposed ACU are superior to a basic four-bit digital Arithmetic Logic Unit (ALU). Obviously, the calculation ability of presented ACU is higher than the simple four-bit ALU which processes only several basic arithmetic and logic functions. The number of transistors of the ACU is only 4.9 % of the minimum estimation of conventional field programmable gate array (FPGA) for arbitrary four-bit calculations. In addition, the static power of the designed ACU is eliminated by using our proposed power-gating scheme.