Abstract
The design of an interconnection network (ICN) for a scalable multiprocessor system is presented. The tree-structured network (called SHUNT for scalable hierarchical unidirectional network topology) is organized so that it can be scaled not only in width (through the use of bit slicing), but also in number of ports and in data transfer speed. The network is made from three custom chip types: cluster controller, crossbar switch, and network interface. Implementation of the first prototype chips in 2- mu m CMOS is discussed, and the results of detailed circuit simulations for GaAs implementations are given. The network is fault tolerant and is able to detect and correct all single-bit transmission errors. In addition, it can detect failures and reconfigure to work around problems in controllers, port interfaces, or user processors. The network is part of the experimental decoupled computer architect project (DART) currently under study and development.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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