Abstract
An 8-kb (128-word*64-b) CMOS associative memory with word- and bit-parallel operation is described. The highly parallel and pipelined architecture is optimized for high-speed associative operations. The data processing capability is one word/cycle corresponding to 16 MIPS at a typical cycle time of 60 ns. The memory is fault tolerant under software control. A faulty word location in the memory can be made inaccessible by on-chip circuitry. The device is a complete single-chip associative memory with internally controlled addressing and associative data as output.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
