A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Yi Yu,Shushan Qiao,Yong Hei,Jia Yuan

doi:10.3390/electronics8121422

Abstract

To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

Highlights

Internet of Things (IoT), mobile and medical application have urge the Very Large Scale Integrated circuites (VLSI) designer to build ultra-low power (ULP) circuits [1,2]
Literature [14] proposed a Digital Low-Dropout (DLDO) controlled by phase-locked clock, which achieves a fast transient response, but the stacking of power PMOS causes a drop of current efficiency and make it unable to work at very low voltages
This paper proposes a DLDO based on adaptive clock technique which achieves a fast transient response with low supply ripple and a high current efficiency

Summary

Introduction

Internet of Things (IoT), mobile and medical application have urge the Very Large Scale Integrated circuites (VLSI) designer to build ultra-low power (ULP) circuits [1,2]. Since only one PMOS is turned on/off per clock cycle, the transient response time of this DLDO is mainly determined by its sample frequency Fs. Increasing Fs can reduce the transient response time, but the negative impact is a larger steady-state power consumption and lower current efficiency. Literature [14] proposed a DLDO controlled by phase-locked clock, which achieves a fast transient response, but the stacking of power PMOS causes a drop of current efficiency and make it unable to work at very low voltages. A DLDO combined coarse-tuning and fine-tuning (CFT) proposed by [15] makes a good tradeoff between power consumption and transient response time, but it needs two clock, which make a large area overhead. This paper proposes a DLDO based on adaptive clock technique which achieves a fast transient response with low supply ripple and a high current efficiency.

Proposed Technique

Design Consideration

Experiments

Conclusions