Abstract
A 1.8-V, 150-mA fast settling low dropout linear regulator (LDO) with single Miller compensation capacitor is presented. By utilizing the digital-controlled dynamic bias circuit to track the output current, the proposed LDO provides fast settling time for the output capacitors with low and high equivalent series resistance (ESR). The proposed LDO has been fabricated in a 0.35-mum 2P4M CMOS technology, and the active chip area is 480mum times 675mum. The measurement results show the settling time of 4mus can be achieved with 0.5% error for full load-current changes for both multilayer ceramic and electrolytic 1-muF output capacitors. Furthermore, the line and load regulations are 0.127%N and 40ppm/mA, respectively. The dropout voltage is 190mV in 150mA output current. The measured quiescent current is 45muA in 5V supply voltage without output current
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
