A Fast Nonlinear Timing Analysis Method for Nanometer Technologies

Abstract

Timing analysis method needs to be both accurate and efficient, especially for the submicron VLSI circuit designs. In this paper, a fast high-accuracy timing analysis method is presented. Nonlinear current-based cell delay model is utilized, which can achieve the goal of accurate nanometer timing including voltage and temperature variation. At the same time, we choose a quick reduced-order network model to keep this method efficient. Experimental results in a 90 nm technology show that the delays are accurately estimated, while the running time and memory cost is at a low level.