Abstract
An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.
Highlights
As the demand for high-speed off-chip I/O bandwidth in computing systems increases, the importance of energy efficiency of serial links is rapidly increasing
Instead of using a phase-locked loops (PLLs), we introduce a clock multiplier technology that uses a digital multiplying delay-locked loop (MDLL) to obtain fast lock characteristics
The proposed MDLL has been implemented in a 65-nm CMOS process
Summary
As the demand for high-speed off-chip I/O bandwidth in computing systems increases, the importance of energy efficiency of serial links is rapidly increasing. One of the most critical building blocks in this high-speed energy proportion link design is a fast power-on (or fast lock) clock multiplier for burst-mode operation. Clock multipliers have been designed based on phase-locked loops (PLLs). Among the PLLs showing reasonable power and performance, the digital PLL from [6] achieved a lock time of forty reference clock cycles, which is insufficient for use in burst mode serial link applications. It consists of a multiplexer (MUX), a multiplexed ring. Electronics 2021, 10, 177 shows the block diagram of a typical MDLL It consists of a multiplexer (MUX), a multiplexed ring oscillator (MRO), a phase detector (PD), a charge pump (CP) + loop filter (LF), a diovsidcielrlaNto,ra(nMdRaOs)e,laecpthloagseicd. Talhl-ids iigsithaleMfirDstLfLastthlaotcfkeatlul-rdeisgiataclyMcliDcLVLertnhiaetruTtiDliCzes a to achyicelivceVfearsnt ipeorwarecrh-oitnecctaupraeb[i2li0t–y2. 6T]htios aischthievfeirsatwfaisdtelodcekteacltl-iodnigritaanlgMe DanLdLhthigaht uretisloizluestion. a cyTclhiceVresrtnioefr tahricshipteacpteurreis[2o0r–g2a6n]itzoedacahsiefvoellaowisd. eSdeecteioctnio2nprarensgeenatsndthheigahrcrheistoelcututiroen.and Theorpeesrtaotfiotnhiosfptahpeeprriospoorsgeadnaizlle-diagsitafol lMloDwLs.LS, eScetcitoinon23psrhesoewnstsththeeexaprcehrimtecetnutrael raensdulotsp,-and eratSioenctioofnth4epprersoepnotsetdhealclo-dnicgluitsailoMn.DLL, Section 3 shows the experimental results, and Section 4 presents the conclusion
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