Abstract
Embedded block coding, i.e., embedded block coder with optimal truncation (EBCOT) tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle-efficient context formation. These pass-parallel architectures require that JPEG2000's three mode switches be turned on; thus, coding efficiency is sacrificed for improved throughput. In this paper, a new fast EBCOT tier-1 design is presented: It is called the split arithmetic encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using the following three methods: clock cycle estimation, multithreaded software implementation, and FPGA hardware implementation. All three methods achieve throughput improvement; the hardware implementation exhibits the largest speedup, as expected. The benefits of evaluating a proposed process (algorithm) from different perspectives are illustrated.
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