Abstract
This thesis introduces a novel approach to rapid Design Space Exploration (DSE) and presents a formalized High Level Synthesis (HLS) design flow with multi parametric optimization issues related to DSE such as the precision of evaluation, time exhausted during evaluation and also automation of the exploration process. During DSE a conflicting situation always exists for the designer to concurrently maximize the accuracy of the exploration process and minimize the time spent during DSE analysis. This technique is capable of drastically reducing the number of architectural variants to be analyzed for accurate selection of the optimal design point in a short time. The DSE results for many benchmarks are presented along with a comparison to an existing DSE approach that uses the hierarchical structure method for architecture evaluation. Results indicated significant improvement in speedup compared to the current existing approach.
Highlights
The design and development of systems with heterogeneous performance optimization objective requires extensive analysis and assessment of the design space, due to the assorted nature of the parameters, and due to the diversity in architecture for implementation
Investigations of the results reveal that the proposed approach is capable of drastically improving the acceleration time for finding the optimal architecture compared to the current approach shown in [2]
After the architectural design points were organized in increasing and decreasing order based on the priority factor calculated, the procedure for applying the search algorithm became very simple
Summary
The design and development of systems with heterogeneous performance optimization objective requires extensive analysis and assessment of the design space, due to the assorted nature of the parameters, and due to the diversity in architecture for implementation. High level synthesis is a methodology of transforming an algorithmic behavioral description into an actual Register Transfer Level (RTL) structure. High level synthesis methodology contains a sequence of tasks to convert the abstract behavioral description of the algorithm into its respective structural block at RT level. A description of the algorithm is usually represented in the form of an acyclic directed graph known as a sequencing graph [14] These graphs specify the input/output relation of the algorithm and the data dependency present in the data flow. High level synthesis is a conversion from the abstract behavioral description to its respective hardware description in the form of memory elements, storage units, multiplexers/demultiplexers and the necessary interconnections. The step is to apply high level transformation techniques with the aim of optimizing the behavior as per the desired performance. In order to realize the structure, the final step is to perform scheduling to determine the time at which each operation is executed and the allocation, which is synthesizing the necessary hardware to perform the operations
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