Abstract
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and routability. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach which allows wires to have bounded-, length detours to bypass congestions. Our method is more realistic and precise than the previous work. It is much faster than a global router for estimation purpose. The experimental results demonstrate the effectiveness of the method on routing benchmarks.
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