Abstract
A noble automatic frequency calibration (AFC) scheme is proposed for phase-locked loop (PLL) based frequency synthesizer. For fast AFC operation, the frequency control code is updated right after the frequency difference is detected. The uncertainty of the phase relationship between the reference clock and VCO output is eliminated by comparing the divided VCO clock with two-phase reference clocks. The AFC is applied to a CMOS frequency synthesizer. The measured worst case AFC time is less than 1.6µs. The AFC circuit implemented in a 0.18µm CMOS process occupies 0.01mm2. The phase noise of the frequency synthesizer output is −113dBc/Hz at 1MHz offset from the 4GHz carrier. The whole frequency synthesizer consumes 23mW from a 1.8V supply.
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