A Fast and Smooth Single-Phase DSC-Based Frequency-Locked Loop Under Adverse Grid Conditions

Abstract

This article proposes a frequency-locked loop (FLL) with fast and smooth dynamic performance for single-phase grid-connected inverters under adverse grid conditions. Different from modeling with the orthogonal signals of the same amplitudes or modeling with the ideal single-phase signal, the proposed linear frequency estimation model is developed with the difference of signal amplitudes that are generated by cascaded delayed signal cancellation operators. Based on this model, an enhanced variable-step-size least mean square algorithm is proposed to construct the FLL, where a smooth factor and a damping factor are integrated. In addition, the convergence analysis and the parameter tuning are also given. Compared with some well-known methods, the proposed FLL can provide smoother dynamic performance with relatively fast response speed under grid conditions with small frequency deviation or different levels of phase/amplitude jump, which are verified by experiments.