Abstract
Set-partitioning in hierarchical trees (SPIHT) is one of the well-known image compression schemes. SPIHT offers an agreeable compression ratio and produces an embedded bit-stream for progressive transmission. However, the major disadvantage of SPIHT is its large memory requirement. In this paper, we propose a memory efficient SPIHT image coder and its parallel implantation. The memory requirement is reduced without sacrificing image quality. All bit-planes are concurrently encoded in order to speed up the entire coding flow. The result shows that the proposed algorithm is roughly 6 times faster than the original SPIHT. For a 512 × 512 image, the memory requirement is reduced from 5.83Mb to 491Kb. The proposed algorithm is also realized on FPGA. With pipeline design, the circuit can run at 110MHz, which can encode a 512 × 512 image in 1.438ms. Thus, the circuit achieves very high throughput, 182MPixels/sec, and can be applied to high performance image compression applications.
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