Abstract
A 256-channel analog-to-digital converter having a 10 nsec per channel digitizing rate utilizing a 100 Mc crystal controlled clock will be described. Pulse analysis is accomplished by a new technique - a sample of the input pulse is analyzed based on "crossover timing" rather than "peak detection." This technique results in better linearity and less spectrum distortion at high counting rates. The "crossover timing" also provides a means of pile-up rejection based on the input pulse shape. A flexible address control provides a means of digital zero suppression which eliminates the spectrum distortion normally present with analog zero suppression and provides an accurate, reproducible means of analyzing portions of a spectrum. In order to minimize the ADC dead time, address information is "transferred" in parallel to the memory. Immediately after transfer the ADC is "free" to accept another input pulse for analysis. The ADC was designed as a plug-in accessory to a versatile, high speed, thin film memory. The complete system provides a means for accurately accumulating data at analyzed counting rates exceeding 100,000 stored counts per second.
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