Abstract
A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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