A dynamic random instruction and stimulus generation for functional verification of embedded processor

Abstract

An efficient dynamic instruction and stimulus generator and its associated methodology are introduced in this paper. They have been used in the functional verification of a high performance low-power embedded processor. The generator reads in test scripts with a set of predefined syntax and generates random instructions which are fed to the processor. The generator is also used to generate purely random stimuli with one of the five random modes. It can be running forever, until it catches some function bug. This methodology is proved to have significantly reduced verification cycle, improved test coverage, and facilitated developing a complex embedded processor.