A dynamic measurement method for parasitic capacitances of high voltage SiC MOSFETs

Abstract

The voltage dependent parasitic capacitances in high voltage semiconductor power devices such as MOSFET, JFET and IGBT play a vital role in the understanding and modeling of the device switching performance. In this paper, a simple but effective parasitic capacitance measurement method is proposed. The output capacitance C oss and the reverse transfer capacitance C rss can be measured simultaneously and directly in the proposed parasitic capacitance tester (PCT). The input capacitance C iss is measured based on gate driver waveforms during the turn on transient. To verify the effectiveness of the proposed method, a 10kV SiC MOSFET parasitic capacitances are measured as an example. The measured parasitic capacitance results are compared with those from a conventional LCR meter and theoretical calculation. Furthermore, a Matlab/Simulink compact circuit model for the 10kV SiC MOSFET is developed based on the measured parasitic capacitances, whose results also validate the effectiveness of the proposed method.