A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

Abstract

A dual phase frequency detector phase-locked loop (PLL) architecture for multi-lane 5 Gbps serial link receiver is demonstrated using 0.13 mum CMOS. The PLL's 8 multiphase clocks can be rotated altogether digitally with respect to a single fixed phase clock from a main PLL. The phase step resolution is 1/15 of a unit bit interval and the rotation is achieved by adding only one additional phase-frequency detector (PFD) and a charge pump. The rms jitter is 1.2 ps for 5 Gbps serial link operation. The new PLL occupies 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 3 mA from a 1.2 V supply. The small area and low power nature of the architecture is suitable for receivers in multi-lane serial links.