Abstract
This paper presents a dual-path nonuniform blocker tolerant wideband receiver that employs digital harmonic rejection to suppress local oscillator (LO) harmonic interferers. The proposed receiver performs harmonic rejection of any LO harmonic including seventh and ninth using only four uniformly spaced clocks each with 25% duty cycle. An adaptive minimum mean-squared error (MMSE) harmonic rejection equalizer is developed that minimizes the desired signal distortion in the mean-squared error sense in the presence of harmonic interferers and the correlated noise between the two paths. The chip prototype is fabricated in 130 nm CMOS process and achieved harmonic rejection ratio (HRR) >75 dB for LO harmonic interferers up to the measured 11th harmonic. The 3.1 dB noise figure (NF) at 1 GHz frequency, 14.5 dBm out-of-band third-order intermodulation intercept point (OBIIP3) at 80 MHz offset from 1 GHz and higher than 10 dB return loss in the frequency range of 100–1450 MHz is measured for the proposed receiver.
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