A Dual Modular Redundancy Scheme for CPU–FPGA Platform-Based Systems

Abstract

This paper presents a practical view of how to implement a dual modular redundancy (DMR) scheme in a central processing unit–field-programmable gate array (CPU–FPGA) heterogeneous platform-based system, which is also described. FPGAs can be valuable resources when determinism and fast response/acquisition rates are required, while processing large volumes of data. On the other side, CPUs are affordable options for most other processing tasks, especially less frequent tasks, such as data recording. A heterogeneous platform is herein proposed and aims to achieve a reliable, however cost-effective solution. Subsequently, this paper proposes a method to implement a DMR scheme for monitoring systems by means of self-monitoring schemes, health indicators, and a voter that is not a physical switch connected to the monitoring devices, but is software-implemented within the interface system after the data storage system. This proved to be an effective way to deal with disagreements between units when an even number of units are being used, thus not being possible to use a majority-based voting system. The implemented design was thoroughly tested, showing effectiveness in terms of redundancy with improved reliability.