Abstract
Discrete Wavelet Transform (DWT) is widely used in signal processing applications. In this paper, we describe hardware implementation of a lifting-based DWT, which is used in image compression. The CDF(2,2) lifting-based wavelet transform is modeled and simulated using MATLAB. Based on DSP methodologies, the signal flow graph and dependence graph are derived. The dependence graph is optimized and used to implement the hardware description of the circuit in Verilog. We have synthesized and implemented the circuit using both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design approaches. To confirm the circuit operation, post-synthesis and post-layout simulations were done for FPGA and ASIC designs, respectively.
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