A DRAM technology using MIM BST capacitor for 0.15 μm DRAM generation and beyond

Abstract

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.