Abstract

SummaryIn this study, a differential phase‐shift‐keying (DPSK) demodulator, which is implemented by digital circuit, is proposed. A differential voltage clipper is used to generate narrow pulses at the extremum of the received modulated signal. Regarding the DPSK signal, the outputs of the clipper have double frequency. In order to halve the frequency, a frequency divider is applied to get synchronous clock. Two binary counters are used to detect phase variation; the data are recovered after two times sampling. This technique removes the need for voltage controlled oscillator (VCO). The proposed demodulator is postlayout simulated in a 0.18‐μm CMOS process, with a power of 64 μW and active area of 68 × 70 μm2. The demodulator recovers 10 Mb/s data rate at 10‐MHz carrier frequency using a 1.8‐V power supply.

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