Abstract
The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii.The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.
Highlights
Fb−1 after ten years of operation at the HL-Large Hadron Collider (LHC), the ATLAS experiment will continue to explore the origin of the electroweak symmetry breaking mechanism at the highest energy frontier
The Inner Detector (ID) has been designed to operate ten years at the peak luminosity of 1034 cm−2 s−1, its performance will degrade with the cumulated effects of radiation damage and ageing, and it will approach the end of its lifetime by the end of the LHC programme
3.6 Data Acquisition System The Data Acquisition System (DAQ) used for the results presented in this paper is the so-called High Speed Input Output (HSIO), a generic DAQ developed at SLAC to provide signal processing capabilities for various silicon tracking upgrade projects (Pixel and Strips) in ATLAS
Summary
The current prototype of the readout chip is the 128-channel ATLAS Binary Chip (ABCN) produced in 0.25 μm IBM CMOS technology ( the chip will be referred hereafter as ABCN25 [13]). It is very similar to the ABCD3TA chips used in the current ATLAS SCT strip tracker [14] An evolution of this chip using 130 nm IBM CMOS technology (the 256-channel ABCN-13) has been recently submitted for fabrication and is intended for future evolutions of the prototype programme. The ABCN-25 chip receives two clock inputs, the main Bunch-Crossing clock (always running at 40 MHz in synchronization with the beam crossing rate) and the readout clock used for data throughput. The ABCN-25 chip implements a new power management block with two prototypes of distributed shunt regulator circuits for the serial powering scheme, and a low drop voltage regulator to supply the analog front-end voltage from the digital input. Each channel of the front-end has an internal calibration circuit that can be used to inject a test charge into the analogue chain. The resulting values for the input noise and gain (without input load), ∼400 electrons Equivalent Noise Charge (ENC(e)) and 100 mV/fC respectively, are in excellent agreement with the design values of the ASIC
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