Abstract
By adopting the charge-plasma concept, dopingless FETs with metal-semiconductor and metal–insulator–semiconductor (MIS) contacts in parallel at the source/drain (SD) have been studied in this letter. Currents are found to flow mainly through the MIS contacts for a given SD metal workfunction when the insulator thickness is thin enough. In order to avoid the possible penalty caused by Fermi level pinning, the dopingless FET with only SD MIS contacts has been proposed as well. The impacts of insulator material parameters, such as bandgap, electron affinity, dielectric constant, and physical thickness, on the electrical characteristics of the dopingless FET have been investigated systematically. Based on numerical simulations, this letter provides a general guideline with physical insights for designing dopingless FETs with high-permittivity insulator at the SD MIS contacts.
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