Abstract
A high performance, high frequency phase-locked loop (PLL), based on a divider-less structure is presented in this paper. This PLL includes an open-loop phase frequency detector (PFD) and a bulk driven charge pump which is designed by utilizing a 0.18μm CMOS process with a 1.8V power supply. The proposed PLL has a locking range frequency of 2.5–7.3GHz. The rms and peak-to-peak jitters of this PLL at 5GHz are 3.21 and 0.88ps respectively. The total power consumption is approximately 13.4mW.
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