Abstract
Inverters-based islanded microgrids are operated by local digital signal processors, driven by their own local clocks. These local clocks have drifts affecting the clock signals which are used to control the inverters in real time. In this scenario, a steady-state deviation is observed in active power sharing, degrading the microgrid performance. This paper presents a new control scheme that improves the microgrid performance by cancelling the active power sharing error due to clock drifts. The study includes a theoretical stability analysis and a design procedure of the control parameters based on the dynamic characteristics. Finally, selected experimental results are obtained in a laboratory microgrid with four inverters. In this setup, each inverter was equipped with its digital signal processor with drifting local clock.
Highlights
Microgrids (MG) are power systems that integrate a large number of distributed generation units (DG), loads and storage systems using fast acting power inverters [1]
The inverters considered in this study are equipped with their own digital signal processor (DSP) that have an autonomous clock with a local time that differ from each other due to the clock drifts
A deviation is generated in the local frequency in steady state. These local references can be written as a function of the global frequency and the clock drift rates as [25]: ωi∗,ss = di ωss due to the clock drifts and the frequency deviations, the active power injected for each VSI in steady state Pi,ss is different to the ideal active power expressed in Equation (8)
Summary
Microgrids (MG) are power systems that integrate a large number of distributed generation units (DG), loads and storage systems using fast acting power inverters [1]. This study analyses different secondary control policies under drifting clocks, including a closed-loop model for each policy It considers a recent alternative approach for frequency regulation and power sharing named droop-free control [18]. This study considers a distributed averaging control in the secondary layer This base control architecture is modified with a new control term in order to reduce the steady-state active power sharing error produced by the clock drifts. The new control scheme is driven with a communication service that provides accurate active power sharing for all load conditions under the clock drifts
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
