A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies

Abstract

This paper compares area scaling capabilities of many kinds of SRAM margin-assist solutions for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporation of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever-increasing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> random variation (¿ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> )> resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different ¿ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> -increasing scenarios of being pessimistic and optimistic are assumed, where o-vt becomes > 130 mV and suppressed to < 70 mV at the 15-nm process node, respectively. As a result, it has been shown that the 6T SRAM cell will be allowed long reign, even in the 15-nm process node, if ¿ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> can be suppressed to < 70 mV thanks to effective oxide thickness scaling for the low-standby-power process; otherwise, 10T and 8T with read-modify-write will be needed after ¿ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> becomes > 85 and 75 mV, respectively.