Abstract
A discrete-time charge-domain filter (CDF) with bandwidth calibration was proposed for LTE application. The CDF, based on feedback gain and delay, could suppress sinc distortion to achieve a like brick-wall filtering. Moreover, CDF with non-decimation and multi-stage topology could overcome the noise-folding issue and save chip area. The measurement showed that CDF performed a >59dB adjacent channel rejection (ACR), >85dB stop-band attenuation, and 5-to-26 MHz reconfigurable bandwidth. The chip also possessed 41dB conversion gain under 7mA current from a 1.2V power supply. The chip, including whole CDF and clock circuits, occupies 0.52mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65nm CMOS process.
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