A discrete formalization of switch-level circuit behavior

Abstract

In [1], we developed a discrete switch-level circuit model for digital CMOS circuits. It describes the logic behavior - static as well as dynamic - of abstract transistor networks and captures logic faults due to conflicts, nondefined gates, hazards, charge sharing, imperfectness of switches, and relative timing problems. Although the model is directed towards CMOS, it is applicable to every FET technology. It offers a straightforward description of switch-level circuit behavior and a rigorous mathematical framework with which powerful results can be inferred. Due to a stepwise refinement of a basic model, we are able to keep grip on the formalization, can consider each important physical aspect in isolation, and, moreover, can formally compare the notions in the refined models with their counterparts in the basic model. The overview given in this paper concentrates on the main issues of the model, and discusses the major results. For a more detailed discussion of the model, a more detailed motivation of the choices made, and proofs of the results obtained, we refer to [1].